groovylight/verilog/coordinator.sv

module coordinator (
    input clk
);

  // pixgen signals
  reg pixgen_start;
  reg [8:0] x;
  reg [8:0] y;
  wire [23:0] pix_rgb[2];
  wire [1:0] pix_done;

  pixgen pix0 (
      .clk(clk),
      .start(pixgen_start),
      .x(x),
      .y(y),
      .rgb(pix_rgb[0]),
      .done(pix_done[0])
  );
  pixgen pix1 (
      .clk(clk),
      .start(pixgen_start),
      .x(x),
      .y(y + 9'd32),
      .rgb(pix_rgb[1]),
      .done(pix_done[1])
  );


  // slicer signals
  wire bitslice_start;
  wire [5:0] bitplane_data;
  wire [10:0] bitplane_addr;
  wire bitplane_wren;
  wire bitplane_done;

  bitslicer bslice (
      .clk(clk),
      .rgb(pix_rgb),
      .pixnum(x),
      .start_write(bitslice_start),
      .bitplane_data(bitplane_data),
      .bitplane_addr(bitplane_addr),
      .bitplane_wren(bitplane_wren),
      .done(bitplane_done)
  );

  // bram signals

  wire [8:0] din;
  wire [10:0] addr_w;
  wire [8:0] dout;
  wire [10:0] addr_r;
  wire read_clk;
  wire write_clk;

  lineram bram (
      .write_clk(clk),
      .read_clk(clk),
      .addr_w(bitplane_addr),
      .din({3'b000, bitplane_data}),
      .write_en(bitplane_wren),
      .addr_r(addr_r),
      .dout(dout)
  );

  // driver
  reg write_line;
  wire line_done;
  wire [2:0] panel_rgb0;
  wire [2:0] panel_rgb1;
  wire display_clk;
  wire out_enable;
  wire latch;

  hub75e driver (
      .clk(clk),
      .write_trig(write_line),
      .panel_rgb0(panel_rgb0),
      .panel_rgb1(panel_rgb1),
      .display_clk(display_clk),
      .out_enable(out_enable),
      .latch(latch),
      .done(line_done),
      .pixbuf_addr(addr_r),
      .pixbuf_data(dout)
  );


  reg [4:0] state = 0;

  localparam unsigned StateInit = 0;
  localparam unsigned StateStartFrame = 1;
  localparam unsigned StateGenerateLine = 2;
  localparam unsigned StateShowLine = 3;
  localparam unsigned StateIncrementLine = 4;
  // we're gonna try this
  assign bitslice_start = pix_done[0] & pix_done[1];  // bitslice start when both pix done.

  always @(posedge clk) begin
    case (state)
      StateInit: begin
        x <= 0;
        y <= 0;
        state <= StateStartFrame;
      end
      StateStartFrame: begin
        pixgen_start <= 1;
        state <= StateGenerateLine;
      end
      StateGenerateLine: begin
        pixgen_start <= 0;
        if (bitplane_done) begin
          if (x < 127) begin
            x <= x + 1;
            pixgen_start <= 1;
            // generate next
          end else begin
            write_line <= 1;
            state <= StateShowLine;
          end
        end
      end
      StateShowLine: begin
          write_line <= 0;
          if (line_done) begin
            state <= StateIncrementLine;
          end
      end
      StateIncrementLine: begin
        x <= 0;
        y <= y + 1;
        if (y == 31) begin
          state <= StateInit;
        end else begin
          state <= StateStartFrame;
        end
      end
      default: state <= StateInit;
    endcase
  end


endmodule