groovylight/verilog/tb/bitslicer_tb.sv

`timescale 1ns / 100ps  // 1 ns time unit, 100 ps resolution

module bitslicer_tb;
  reg clk = 0;

  reg [23:0] rgb_in [2];
  reg start_write = 0;
  reg [7:0] pixnum = 0;
  wire [5:0] bitplane_data;
  wire [10:0] bitplane_addr;
  wire bitplane_wren;
  wire done;

  bitslicer dut(
    .clk(clk),
    .rgb(rgb_in),
    .pixnum(pixnum),
    .start_write(start_write),
    .bitplane_data(bitplane_data),
    .bitplane_addr(bitplane_addr),
    .done(done)
  );

  always #5 clk = !clk;
  initial begin
    $dumpfile("bitslicer_tb.vcd");
    $dumpvars(0, bitslicer_tb);
    rgb_in[0] <= 24'hEE8833;
    rgb_in[1] <= 24'hDD7722;
    pixnum <= 3;
    @(posedge clk);
    start_write <= 1;
    @(posedge clk);
    start_write <= 0;
    @(done);
    repeat (10) @(posedge clk);
    $finish();
  end
  initial begin
    repeat (100000) @(posedge clk);
    $finish();
  end
endmodule