generated from saji/ecp5-template
205 lines
5.2 KiB
C++
205 lines
5.2 KiB
C++
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// Common Verilator Simulation/test constructs.
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// Includes a simulation-fixture useful for writing tests.
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#pragma once
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include <cstdint>
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#include <span>
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#include <memory>
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#include <queue>
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#include <vector>
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// represents a generic co-simulated device.
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// While this abstract class is very simple, it enables dynamic behavior to be added to the
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// simulation fixture.
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class CosimulatedDevice {
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public:
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virtual ~CosimulatedDevice(){};
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virtual void tick() = 0;
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};
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// Simple stimulus class used to trigger basic operations
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class PulseStimulus : public CosimulatedDevice {
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unsigned long width;
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unsigned char &signal;
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unsigned long counter = 0;
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public:
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PulseStimulus(unsigned char &signal, unsigned long width) : signal(signal) {
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this->width = width;
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}
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virtual void tick() override {
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if (counter < width) {
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signal = 1;
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} else {
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signal = 0;
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}
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counter++;
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}
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};
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class FakeBRAM : public CosimulatedDevice {
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std::array<unsigned long, 512> ram{};
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std::queue<unsigned long> addr_lookup_q;
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unsigned short &addr_in;
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unsigned long &data_out;
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unsigned char &clk;
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public:
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FakeBRAM(int latency, unsigned char &clk, unsigned short &addr_in,
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unsigned long &data_out)
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: addr_lookup_q(), addr_in(addr_in), data_out(data_out), clk(clk) {
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for (int i = 0; i < latency; i++) {
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addr_lookup_q.push(0);
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}
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for (int i = 0; i < ram.size(); i++) {
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ram[i] = i + 3;
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}
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};
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FakeBRAM(int latency, unsigned char &clk, unsigned short &addr_in,
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unsigned long &data_out, std::array<unsigned long, 512> ram)
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: addr_lookup_q(), addr_in(addr_in), data_out(data_out), clk(clk),
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ram(ram) {
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for (int i = 0; i < latency; i++) {
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addr_lookup_q.push(0);
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}
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}
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void tick() {
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// we push and pop in the same tick: this way we keep the queue the same
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// size, acting as a pipeline delay.
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addr_lookup_q.push(addr_in);
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auto addr_to_load = addr_lookup_q.front();
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addr_lookup_q.pop();
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data_out = ram.at(addr_to_load);
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}
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// TODO: allow accessing/setting the data
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const std::span<uint64_t, 512> get() { return this->ram; }
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void write(unsigned short addr, unsigned long data) { ram[addr] = data; }
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};
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// test fixture to reduce amount of runtime code.
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// Supports:
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// adding external modules
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// running the test
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// storing if the done flag was raised (or not)
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//
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// TODO: tracing.
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template <typename DUT> class VerilatorTestFixture {
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public:
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enum class FinishReason { Ok, Timeout };
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private:
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// we call .tick() on all of these. They are bound externally to the DUT.
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std::vector<std::shared_ptr<CosimulatedDevice>> external_devices;
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std::unique_ptr<VerilatedContext> ctx;
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std::unique_ptr<DUT> dut;
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unsigned long timeout =
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1000000; // clock cycles to execute before ending the simulation.
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unsigned long simtime = 0;
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unsigned long posedge = 0;
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// stores the termination-condition for the simulation.
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// if false, it means we timed out. If true, our done_condition returned true.
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enum FinishReason reason;
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typedef std::function<bool(DUT &, unsigned long)> done_callback;
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// callback function to determine execution completion.
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// This can be used to add arbitrary finish-conditions to the execution.
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// If the function returns true, we set the done_set boolean to true;
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done_callback done_check;
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std::unique_ptr<VerilatedVcdC> trace;
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public:
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// Create a new test fixture with a given timeout. Everything else (including
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// done-condition) can be set later.
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VerilatorTestFixture() {
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ctx = std::make_unique<VerilatedContext>();
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dut = std::make_unique<DUT>(ctx.get(), "dut");
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dut->eval(); // let values settle before adding modules.
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}
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void set_timeout(unsigned long new_timeout) { this->timeout = new_timeout; }
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void set_done_callback(done_callback d) { this->done_check = d; }
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void add_module(std::shared_ptr<CosimulatedDevice> device) {
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external_devices.push_back(device);
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}
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void enable_trace(std::string name) {
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if (!trace) {
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ctx->traceEverOn(true);
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trace = std::make_unique<VerilatedVcdC>();
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dut->trace(trace.get(), 99);
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trace->open(name.c_str());
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}
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}
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void exec() {
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bool done = false;
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dut->eval(); // pre-eval.
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while (!done) {
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dut->clk ^= 1;
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dut->eval();
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if (trace) {
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trace->dump(10 * simtime);
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}
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if (dut->clk == 1) {
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posedge++;
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}
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if (done_check) {
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if (done_check(*dut, posedge)) {
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reason = FinishReason::Ok;
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done = true;
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}
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}
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if (posedge >= timeout) {
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reason = FinishReason::Timeout;
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done = true;
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}
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// run our external devices
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for (auto dev : external_devices) {
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dev->tick();
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}
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if (trace) {
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trace->dump(10 * simtime + 5);
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}
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dut->eval(); // allow combinational logic to settle if it's being set on
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// the negative clock.
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if (trace) {
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trace->dump(10 * simtime + 6);
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}
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simtime++;
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}
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if (trace) {
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// close the trace.
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trace->close();
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}
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}
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// return a reference to the DUT itself. Useful for bespoke tests.
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const DUT &get() { return *dut; }
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const FinishReason get_reason() { return reason; }
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};
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